Our website uses cookies provided by us and third parties. Some cookies are necessary for the operation of the website, and you can adjust other cookies at any time, especially those that help us understand the performance of the website, provide you。

I accept
Name:
Phone Number:
Company Name:
mailbox:
Content:
Contact Us
Send Email
English
  • 全球-简体中文
  • Global-English
  • Test Solution

    Wafer High And Low Temperature Test Scheme

    Wafer High And Low Temperature Test Scheme

    1.1.1.Technical Background

    With the development of aerospace technology, some of the high reliability and high performance semiconductor devices, especially the core aerospace components, has become a measure of a country the important symbol of the levels of aerospace science and technology but because of China's integrated circuit industry foundation is weak, the semiconductor device mainly rely on import, not only the high cost of import channels without quality assurance, more there is great potential safety hazard, such as chip implanted trojans structure for this, must have their own research and development at the core of the device.

    1.1.2.Needs And Challenges

    In the chip development and manufacturing process, in order to ensure that the device can withstand the harsh environment such as cold black and hot vacuum magnetic particle photon radiation in space, it is necessary to create a high temperature and low temperature vacuum magnetic field, light particle irradiation and other environment for the device, and then let the device work in it to observe whether the electrical parameters of the device are normal under different environments.

    1.1.3.Solution
    © 2020 SEMISHARE CO., LTD. All Rights Reserved.ICP 19119103